3 people e87e09a50a [Feat] dnnl build for AVX2 W8A8 Int8 (#41318) ...

Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>

2026-05-06 15:28:02 +08:00

..

micro_gemm

[Bugfix] Correct mistake in chained comparison in static assert logic (#38699)

2026-04-07 18:24:39 +08:00

sgl-kernels

[CPU] Add FP8 W8A16 linear support (#41186)

2026-05-06 07:05:27 +00:00

activation_lut_bf16.cpp

[perf][cpu] Accelerate BF16 GELU with LUT impl on Arm CPUs (#37469)

2026-04-15 22:26:17 -07:00

activation.cpp

[Kernel][CPU] Add Quick gelu to CPU (#5717)

2024-06-21 06:39:40 +00:00

cpu_arch_macros.h

[CPU] Added faster exp routine for lower precision data types. (#38112)

2026-04-23 13:14:44 +00:00

cpu_attn_amx.hpp

[Feat] CPU fp8 attn for AMX/AVX-512 (#39445)

2026-04-29 20:43:21 +08:00

cpu_attn_fp8.hpp

[Feat] CPU fp8 attn for AMX/AVX-512 (#39445)

2026-04-29 20:43:21 +08:00

cpu_attn_impl.hpp

[Hardware][Power]Add Power VSX Attention Backend and fix l2 Cache Crash (#40451)

2026-05-04 20:51:09 -07:00

cpu_attn_neon_bfmmla.hpp

[Feat] CPU fp8 attn for AMX/AVX-512 (#39445)

2026-04-29 20:43:21 +08:00

cpu_attn_neon.hpp

[Feat] CPU fp8 attn for AMX/AVX-512 (#39445)

2026-04-29 20:43:21 +08:00

cpu_attn_vec16.hpp

[Feat] CPU fp8 attn for AMX/AVX-512 (#39445)

2026-04-29 20:43:21 +08:00

cpu_attn_vec.hpp

[Hardware][Power]Add Power VSX Attention Backend and fix l2 Cache Crash (#40451)

2026-05-04 20:51:09 -07:00

cpu_attn_vsx.hpp

[Hardware][Power]Add Power VSX Attention Backend and fix l2 Cache Crash (#40451)

2026-05-04 20:51:09 -07:00

cpu_attn_vxe.hpp

[Feat] CPU fp8 attn for AMX/AVX-512 (#39445)

2026-04-29 20:43:21 +08:00

cpu_attn.cpp

[Hardware][Power]Add Power VSX Attention Backend and fix l2 Cache Crash (#40451)

2026-05-04 20:51:09 -07:00

cpu_fused_moe.cpp

[CPU] Support gelu act in cpu_fused_moe (#38770)

2026-04-02 14:14:32 +08:00

cpu_types_arm.hpp

[Fix] Add missing stubs from cpu fp8 attention changes (#41387)

2026-05-06 12:16:27 +08:00

cpu_types_riscv_defs.hpp

[CPU][RISC-V] Support multiple RVV VLEN targets via compile-time dispatch (#39478)

2026-04-20 14:36:59 +08:00

cpu_types_riscv_impl.hpp

[Bugfix][CPU][RISC-V] Clamp exp() input to prevent NaN (#40428)

2026-04-22 09:38:18 +00:00

cpu_types_riscv.hpp

[CPU][RISC-V] Support multiple RVV VLEN targets via compile-time dispatch (#39478)

2026-04-20 14:36:59 +08:00

cpu_types_scalar.hpp

[Fix] Add missing stubs from cpu fp8 attention changes (#41387)

2026-05-06 12:16:27 +08:00

cpu_types_vsx.hpp

[Fix] Add missing stubs from cpu fp8 attention changes (#41387)

2026-05-06 12:16:27 +08:00

cpu_types_vxe.hpp

[Fix] Add missing stubs from cpu fp8 attention changes (#41387)

2026-05-06 12:16:27 +08:00

cpu_types_x86.hpp

[Feat] dnnl build for AVX2 W8A8 Int8 (#41318)

2026-05-06 15:28:02 +08:00

cpu_types.hpp

feat: add RISC-V support for CPU backend (v2) (#36578)

2026-03-10 21:51:39 -07:00

cpu_wna16.cpp

[Doc]: fixing multiple typos in diverse files (#33256)

2026-01-29 16:52:03 +08:00

dnnl_helper.cpp

[Perf] Use dummy M for weight prepacking on x86 (#35890)

2026-03-05 04:56:49 +00:00

dnnl_helper.h

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

dnnl_kernels.cpp

[Feat] dnnl build for AVX2 W8A8 Int8 (#41318)

2026-05-06 15:28:02 +08:00

float_convert.hpp

[Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112)

2025-09-25 20:46:11 +08:00

generate_cpu_attn_dispatch.py

[Hardware][Power]Add Power VSX Attention Backend and fix l2 Cache Crash (#40451)

2026-05-04 20:51:09 -07:00

layernorm.cpp

[Kernel][Misc] Use TORCH_LIBRARY instead of PYBIND11_MODULE for custom ops (#5047)

2024-06-09 16:23:30 -04:00

mla_decode.cpp

[CPU] Enable FP16 (Half dtype) support for s390x (#34116)

2026-02-11 14:41:42 +08:00

pos_encoding.cpp

[Feat] DeepSeek V4 Rebased (#40860)

2026-04-26 18:31:08 -07:00

shm.cpp

[Bugfix][CPU] Fix thread num for shared memory communication (#33317)

2026-01-29 03:26:58 -08:00

spec_decode_utils.cpp

feat(cpu): add CPU support for draft model speculative decoding (#32662)

2026-04-10 11:49:52 +08:00

torch_bindings.cpp

[Feat] dnnl build for AVX2 W8A8 Int8 (#41318)

2026-05-06 15:28:02 +08:00

utils.cpp

[CPU] Refactor CPU affinity and memory management (#39781)

2026-04-17 21:01:08 +08:00

utils.hpp

[Hardware][Power]Add Power VSX Attention Backend and fix l2 Cache Crash (#40451)

2026-05-04 20:51:09 -07:00