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ebfbcfe46a
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Stop setting CUDA_VISIBLE_DEVICES internally in vLLM, add device_ids arg (#45026)
Signed-off-by: Tyler Michael Smith <tlrmchlsmth@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Codex <codex@openai.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: kourosh hakhamaneshi <kouroshHakha@users.noreply.github.com>
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2026-06-20 13:38:10 -07:00 |
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JasonLi314andGitHub
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93bad11912
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[Bugfix] Fix gridDim.y overflow for large row counts (#45255)
Signed-off-by: Jason Li <li.jason.cs@gmail.com>
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2026-06-19 23:27:45 -04:00 |
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Chris LeonardandGitHub
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b9a7cd464c
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[12/n] final _C library kernel migration (#45415)
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2026-06-19 06:57:26 -07:00 |
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Wentao YeandGitHub
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225936a1dd
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[CI Bug] Revert #42379 to fix CI Multi-Modal Models (Extended Generation 1) (#46070)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-06-18 12:37:39 -07:00 |
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HumphreyandGitHub
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4583630b56
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[Bugfix][Kernel] Check output alignment in vectorize_with_alignment (fixes misaligned-address crash for non-multiple-of-8 head sizes) (#45466)
Signed-off-by: HumphreySun98 <humphreysun98@gmail.com>
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2026-06-18 16:58:22 +00:00 |
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021cdf72bc
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Fix _riscv_supports_rvv_vlen128() to detect RVV on hardware without zvl flags (#43179)
Signed-off-by: liuyudong <liuyudong@iscas.ac.cn>
Co-authored-by: YuanSheng <yuansheng@isrc.iscas.ac.cn>
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2026-06-18 21:22:35 +08:00 |
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Jee Jee LiandGitHub
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22cc891108
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[Kernel] Add PDL support for DeepGEMM kernel (#46006)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-06-18 20:49:01 +08:00 |
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afdcbd5d39
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[ROCm][DSv4] Functional fixes for DeepSeek V4 on MI300X/MI325X (#45681)
Signed-off-by: ganyi <ygan@amd.com>
Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com>
Signed-off-by: Tuukka Sarvi <tuukka.sarvi@amd.com>
Co-authored-by: ganyi <ygan@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Markus Hartikainen <markus.hartikainen@amd.com>
Co-authored-by: Jin Tao <jintao12@amd.com>
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2026-06-18 12:21:14 +00:00 |
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Micah WilliamsonandGitHub
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e945169207
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Revert "[Kernel] Add PDL support for DeepGEMM kernel" (#45999)
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2026-06-17 22:59:48 -07:00 |
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b4c80ec0fd
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[Refactor] Remove dead cutlass mxfp8 code (#44681)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: Shengqi Chen <harry-chen@outlook.com>
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2026-06-17 21:18:25 -07:00 |
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Jee Jee LiandGitHub
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4403af8fb5
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[Kernel] Add PDL support for DeepGEMM kernel (#42996)
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-06-17 20:37:17 -07:00 |
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arghyadeep sarkarandGitHub
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93bbe94d3a
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[Kernel] Add weightless RMSNorm CUDA kernels for has_weight=False (#41430) (#44109)
Signed-off-by: hello-args <args.sarkar@gmail.com>
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2026-06-16 23:45:55 -07:00 |
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4c62663315
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[M3] Enable FP8 sparse GQA (#45744)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
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2026-06-16 21:38:03 -07:00 |
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Li, JiangandGitHub
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a7fdfeef72
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[CPU] Support Gemma Diffusion (#45690)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-06-16 14:39:56 +08:00 |
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+1
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0a1c5034f5
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[Model] Add MiniMax M3 support (#45381)
Signed-off-by: youkaichao <youkaichao@gmail.com>
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
Signed-off-by: Bugen Zhao <i@bugenzhao.com>
Signed-off-by: Jee Jee Li <pandaleefree@gmail.com>
Signed-off-by: functionstackx <47992694+functionstackx@users.noreply.github.com>
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
Signed-off-by: Jee Jee Li <jeejeelee@inferact.ai>
Co-authored-by: OpenAI Codex <codex@openai.com>
Co-authored-by: Isotr0py <mozf@mail2.sysu.edu.cn>
Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Bugen Zhao <i@bugenzhao.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
Co-authored-by: Roger Wang <hey@rogerw.io>
Co-authored-by: functionstackx <47992694+functionstackx@users.noreply.github.com>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
Co-authored-by: Jee Jee Li <jeejeelee@inferact.ai>
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2026-06-16 01:01:25 +08:00 |
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5ed15f42b9
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Fix the E8M0 scale computation in the MXFP4 (W4A4) MOE CUTLASS kernel (#43557)
Signed-off-by: Xin He <xin3.he@intel.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
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2026-06-15 06:04:54 -07:00 |
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Li, JiangandGitHub
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8760f972ca
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[CPU] Refine CPU attention frontend (#45391)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-06-14 19:26:54 -07:00 |
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78e7293bb1
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[Build] Fix CUDA arch build coverage gaps (#45277)
Signed-off-by: Shengqi Chen <harry-chen@outlook.com>
Co-authored-by: Xin Li <xinli-sw@users.noreply.github.com>
Co-authored-by: ShawRong <ShawRong@users.noreply.github.com>
Co-authored-by: Change72 <Change72@users.noreply.github.com>
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2026-06-13 22:09:20 -07:00 |
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71b961dd35
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[Perf] SM90 cutlass fp8 mm supports odd M by swap_ab, 180~290% kernel performance improvement (#44572)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-06-13 12:05:45 -07:00 |
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Isotr0pyandGitHub
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6635279d8a
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[Migration] Migrate GGUF quantization support to plugin (#39612)
Signed-off-by: Isotr0py <mozf@mail2.sysu.edu.cn>
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2026-06-12 12:02:21 -07:00 |
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a014dddbaa
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[11b/n] Migrate Machete kernels to torch stable ABI (#45304)
Signed-off-by: Chris Leonard <chleonar@redhat.com>
Signed-off-by: Shengqi Chen <harry-chen@outlook.com>
Co-authored-by: Shengqi Chen <harry-chen@outlook.com>
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2026-06-12 10:36:49 +00:00 |
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Chris LeonardandGitHub
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7021be66e8
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[11a/n] Migrate Marlin kernels to torch stable ABI (#45176)
Signed-off-by: Chris Leonard <chleonar@redhat.com>
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2026-06-11 21:22:37 -07:00 |
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f06aefb4e3
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[CPU] Add missing scalar fallback for CPU W4A8 INT4 GEMM (#44523)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: lyd1992 <liuyudong@iscas.ac.cn>
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2026-06-11 08:52:01 +00:00 |
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Juan Pérez de AlgabaandGitHub
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f219788f91
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[Security] Fix info disclosure via int32 truncation in GGUF dequantize kernels (#44971)
Signed-off-by: jperezde <jperezde@redhat.com>
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2026-06-11 08:05:14 +00:00 |
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6e64c1bab1
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[10c/n] Migrate MoE kernels to torch stable ABI (#44565)
Signed-off-by: Chris Leonard <chleonar@redhat.com>
Co-authored-by: Shengqi Chen <harry-chen@outlook.com>
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2026-06-10 23:02:26 -07:00 |
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0b995f8609
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Use std::bit_cast for type punning in CPU kernels (#45089)
Signed-off-by: Yuanyuan Chen <cyyever@outlook.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-10 22:07:44 -07:00 |
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velonica0andGitHub
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f31bc2ea60
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[CPU][RISC-V] Enable oneDNN W8A8 INT8 to run on RISC-V (#44478)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn>
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2026-06-11 04:09:05 +00:00 |
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Micah WilliamsonandGitHub
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e1ed89dbee
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Revert "[Kernel] Speed up silu_and_mul_per_block_quant with warp-shuf… (#45066)
Signed-off-by: Micah Williamson <micah.williamson@amd.com>
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2026-06-09 14:12:06 -07:00 |
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a4b14b98c6
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[Kernel] Speed up silu_and_mul_per_block_quant with warp-shuffle reduction + vectorized I/O (#44173)
Signed-off-by: SII-yangdian <yangdian@sii.edu.cn>
Co-authored-by: SII-yangdian <yangdian@sii.edu.cn>
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2026-06-09 10:41:26 -07:00 |
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Andreas KaratzasandGitHub
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2385e140d6
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[ROCm][CI] Stabilize sleep-mode memory release (#43022)
Signed-off-by: Andreas Karatzas <akaratza@amd.com>
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2026-06-09 16:51:12 +08:00 |
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Charlie FuandGitHub
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228bcc436b
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[ROCm][Kernel] Enable permute_cols for ROCm (#44674)
Signed-off-by: charlifu <charlifu@amd.com>
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2026-06-07 09:50:03 +00:00 |
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bc5745a00f
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[ROCm][MLA] Replace torch.cat in sparse-MLA forward_mqa with fused concat_mla_q (#42838)
Signed-off-by: Markus Hartikainen <markus.hartikainen@amd.com>
Signed-off-by: Frida Andersson <fanderss@amd.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Frida Andersson <fanderss@amd.com>
Co-authored-by: Douglas Lehr <91553416+dllehr-amd@users.noreply.github.com>
Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
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2026-06-06 18:20:50 -05:00 |
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062b05ff3a
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[ROCm][Perf] Fused MoE W4A16 HIP kernel for AMD RDNA3 (gfx1100) (#44075)
Signed-off-by: JartX <sagformas@epdcenter.es>
Co-authored-by: TJian <tunjian.tan@embeddedllm.com>
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2026-06-06 15:30:39 -05:00 |
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TJianandGitHub
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aa6fb8a329
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[Bugfix] [ROCm] [Critical] fallback to regular abi for ROCm (#44648)
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
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2026-06-05 15:51:17 +00:00 |
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Chris LeonardandGitHub
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56aff0dd15
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[10/n] Migrate cuda_view and silu_and_mul_per_block_quant kernels to torch stale ABI. (#44334)
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2026-06-04 20:14:43 -07:00 |
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Yongye ZhuandGitHub
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b5235fca2e
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[DSv4] Adding TRTLLM gen attention kernel (#43827)
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2026-06-04 07:35:09 -07:00 |
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59d0236193
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[10b/n] Migrate custom all-reduce, DeepSeek V4 fused MLA, MiniMax reduce-RMS, and MXFP8 MoE to libtorch stable ABI (#44365)
Signed-off-by: Chris Leonard <chleonar@redhat.com>
Signed-off-by: Shengqi Chen <harry-chen@outlook.com>
Co-authored-by: Shengqi Chen <harry-chen@outlook.com>
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2026-06-04 00:29:46 +08:00 |
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Charlie FuandGitHub
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71df063c49
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Enable perf_token_group_quant/_C_stable_libtorch for ROCm (#42758)
Signed-off-by: charlifu <charlifu@amd.com>
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2026-06-02 23:23:28 -07:00 |
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3099de3617
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[Kernel][MoE] Add GELU_TANH to CPU, CUTLASS, and WNA16 MoE backends (#42027)
Signed-off-by: lesj0610 <lesj0610@users.noreply.github.com>
Co-authored-by: lesj0610 <lesj0610@users.noreply.github.com>
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2026-06-02 17:12:08 -04:00 |
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Chris LeonardandGitHub
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4d93bc35c9
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Migrate header files to torch stable abi (#44013)
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2026-06-02 08:09:52 -07:00 |
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689b0eeb9e
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[HARDWARE][POWER] Enable SHM communicator support for PowerPC (#43754)
Signed-off-by: Rukhaiya <rukhaiya@c643n08aix1-lp1.pok.stglabs.ibm.com>
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
Co-authored-by: Rukhaiya <rukhaiya@c643n08aix1-lp1.pok.stglabs.ibm.com>
Co-authored-by: Akash kaothalkar <61960177+Akashcodes732@users.noreply.github.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-02 18:06:32 +08:00 |
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0b25cf4419
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[CPU][Perf] Enable fused kernels for GDN's gated delta rules (#43534)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-02 08:00:48 +00:00 |
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98f1279815
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[CPU][RISC-V] Add missing RVV cpu_types helpers for WNA16 (#42730)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-01 14:56:41 +08:00 |
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124fac10cb
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[Bugfix] Fix RMSNorm kernels to multiply in weight's native dtype (#42379)
Signed-off-by: Lanze Liu <lanzetech@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-05-29 23:16:53 -07:00 |
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559d6710bf
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[PERF]MiniMax-M2 gate kernel (#38445)
Signed-off-by: Jee Jee Li <pandaleefree@gmail.com>
Signed-off-by: qianlihuang <91178480+qianlihuang@users.noreply.github.com>
Co-authored-by: Yiliu Dong <91178480+qianlihuang@users.noreply.github.com>
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2026-05-29 18:28:34 -07:00 |
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JartXandGitHub
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0cff0741ff
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[Kernel][ROCm] Native W4A16 kernel for AMD RDNA3 (gfx1100) — fp16 + bf16 (#41394)
Signed-off-by: JartX <sagformas@epdcenter.es>
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2026-05-29 11:04:40 +00:00 |
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22a58640b4
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[9/n] Migrate attention and cache kernels to torch stable ABI (continued) (#43717)
Signed-off-by: Chris Leonard <chleonar@redhat.com>
Signed-off-by: Mikayla Gawarecki <mikaylagawarecki@gmail.com>
Co-authored-by: Mikayla Gawarecki <mikaylagawarecki@gmail.com>
Co-authored-by: Shengqi Chen <harry-chen@outlook.com>
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2026-05-29 04:44:45 +00:00 |
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Matthias GehreandGitHub
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a9ec46d4b7
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[ROCm][Perf] Support N=5 in wvSplitK skinny GEMM kernels for speculative decoding (#40687)
Signed-off-by: Matthias Gehre <matthias.gehre@amd.com>
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2026-05-28 16:28:21 +00:00 |
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Wentao YeandGitHub
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64e1218673
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[Perf] Optimize moe permute by pre-allocate buffer, 9~14% kernel performance improvement (#43014)
Signed-off-by: yewentao256 <zhyanwentao@126.com>
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2026-05-28 06:18:26 -07:00 |
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6cc8577421
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[Kernel] Marlin MoE: include SM 12.x in default arch list (#40923)
Signed-off-by: Tony Liu <tonyliu0512@gmail.com>
Co-authored-by: Tony Liu <tonyliu0512@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Shengqi Chen <harry-chen@outlook.com>
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2026-05-28 15:30:26 +08:00 |
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