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5c9f6557d7
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[Hardware][CPU] Enable granite-4 model on cpu (#47641)
Signed-off-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akashkaothalkar@dhcp-9-123-5-76.bl1-in.ibm.com>
Signed-off-by: Akash Kaothalkar <akashkaothalkar@Akashs-MBP.lan>
Signed-off-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@dhcp-9-123-5-76.bl1-in.ibm.com>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@Akashs-MBP.lan>
Co-authored-by: Akash Kaothalkar <akashkaothalkar@akashs-mbp.bl1-in.ibm.com>
Co-authored-by: Akash kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-07-20 06:15:16 +00:00 |
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velonica0andGitHub
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990c2a0187
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[RISC-V] Enable BF16 on VLEN=256 hardware (#45243)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn>
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2026-07-06 06:05:16 +00:00 |
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16f8110935
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[Bugfix][CPU][RISC-V] Fix VLEN detection for RVV attention path (#47532)
Signed-off-by: liutong <liutong@iscas.ac.cn>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-07-06 05:58:03 +00:00 |
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Evgeny ParshutinandGitHub
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bd8d9021ce
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[CPU][Build] Enable oneDNN ITT task collection by default for CPU primitive-level profiling (#47467)
Signed-off-by: Evgeny Parshutin <eugeny.parshutin@intel.com>
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2026-07-03 04:00:19 +00:00 |
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89e99202f2
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[CPU][Perf]Added tanh AOR for faster gelu activations. (#44639)
Signed-off-by: Anna Mayne <anna.mayne@arm.com>
Signed-off-by: almayne <anna.mayne@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-30 23:24:40 -07:00 |
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c6554f321c
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[CPU] Fix macOS/Apple Silicon hang by enabling OpenMP in the build (#46769)
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
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2026-06-26 14:32:21 -04:00 |
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638b1a99cc
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[CPU][RISC-V] Add RVV path for W4A8 INT4 GEMM (#45269)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: lyd1992 <liuyudong@iscas.ac.cn>
Co-authored-by: OpenAI Codex <codex@openai.com>
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2026-06-25 08:18:10 +00:00 |
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Fadi ArafehandGitHub
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061043eaca
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[CPU][Perf] Accelerate unquantized MoE for AArch64 (#46353)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2026-06-24 14:14:35 +00:00 |
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f06aefb4e3
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[CPU] Add missing scalar fallback for CPU W4A8 INT4 GEMM (#44523)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: lyd1992 <liuyudong@iscas.ac.cn>
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2026-06-11 08:52:01 +00:00 |
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velonica0andGitHub
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f31bc2ea60
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[CPU][RISC-V] Enable oneDNN W8A8 INT8 to run on RISC-V (#44478)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn>
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2026-06-11 04:09:05 +00:00 |
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689b0eeb9e
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[HARDWARE][POWER] Enable SHM communicator support for PowerPC (#43754)
Signed-off-by: Rukhaiya <rukhaiya@c643n08aix1-lp1.pok.stglabs.ibm.com>
Signed-off-by: Rukhaiya <bibirukhaiya123@gmail.com>
Co-authored-by: Rukhaiya <rukhaiya@c643n08aix1-lp1.pok.stglabs.ibm.com>
Co-authored-by: Akash kaothalkar <61960177+Akashcodes732@users.noreply.github.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-02 18:06:32 +08:00 |
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0b25cf4419
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[CPU][Perf] Enable fused kernels for GDN's gated delta rules (#43534)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-02 08:00:48 +00:00 |
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98f1279815
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[CPU][RISC-V] Add missing RVV cpu_types helpers for WNA16 (#42730)
Signed-off-by: wcy <233313160abc@gmail.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-06-01 14:56:41 +08:00 |
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f351455f0f
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[CPU][RISC-V] Add RVV-optimized attention kernels for RISC-V Vector Extension (#40119)
Signed-off-by: liuyudong <liuyudong@iscas.ac.cn>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-05-15 12:08:23 +08:00 |
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d6563d693c
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Require C++20 for compatibility with PyTorch (#40380)
Signed-off-by: Richard Barnes <rbarnes@meta.com>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-05-08 22:04:43 -07:00 |
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Li, JiangandGitHub
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b3945cc316
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[CPU] Bump up to the latest CPU kernels (#41924)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-05-07 05:45:59 -07:00 |
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e87e09a50a
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[Feat] dnnl build for AVX2 W8A8 Int8 (#41318)
Signed-off-by: Li, Tianmu <tianmu.li@intel.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-05-06 15:28:02 +08:00 |
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aee190ac37
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[Build] Fall back to system libgomp when torch has no vendored copy (#40575)
Signed-off-by: liuyudong <liuyudong@iscas.ac.cn>
Co-authored-by: Claude <noreply@anthropic.com>
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2026-05-06 11:42:03 +08:00 |
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velonica0andGitHub
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ec7aafc02a
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[CPU][RISC-V] Support multiple RVV VLEN targets via compile-time dispatch (#39478)
Signed-off-by: velonica0 <like@mail.nankai.edu.cn>
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2026-04-20 14:36:59 +08:00 |
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Li, JiangandGitHub
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d02421a7db
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[CPU] Refactor CPU affinity and memory management (#39781)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2026-04-17 21:01:08 +08:00 |
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445b7093fd
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[perf][cpu] Accelerate BF16 GELU with LUT impl on Arm CPUs (#37469)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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2026-04-15 22:26:17 -07:00 |
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Ganesh RandGitHub
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445a2a4d1a
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feat(cpu): add CPU support for draft model speculative decoding (#32662)
Signed-off-by: R <Ganesh.R@amd.com>
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2026-04-10 11:49:52 +08:00 |
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Yintong LuandGitHub
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f09daea261
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[CPU] Support int8 compute mode in CPU AWQ (#35697)
Signed-off-by: Yintong Lu <yintong.lu@intel.com>
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2026-03-31 15:27:37 +08:00 |
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092ace9e3a
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[UX] Improve UX of CPU backend (#36968)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Signed-off-by: Li, Jiang <bigpyj64@gmail.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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2026-03-14 09:27:29 +08:00 |
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4184653775
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feat: add RISC-V support for CPU backend (v2) (#36578)
Signed-off-by: typer-J <2236066784@qq.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-03-10 21:51:39 -07:00 |
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Nikhil GuptaandGitHub
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0a49676fb0
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cpu: aarch64: Upgrade OneDNN for aarch64 to add support for int8 matmul (#36147)
Signed-off-by: Nikhil Gupta <nikhil.gupta2@arm.com>
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2026-03-06 03:48:59 +00:00 |
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90805ff464
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[CI/Build] CPU release supports both of AVX2 and AVX512 (#35466)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: jiang1.li <jiang1.li@intel.com>
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2026-02-28 04:35:21 +00:00 |
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f07a128413
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[CPU][ARM] Add ARM BF16 cross-compilation support and improve documen… (#33079)
Signed-off-by: Maryam Tahhan <mtahhan@redhat.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-02-15 06:33:08 -08:00 |
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R3hankhanandGitHub
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4dffc5e044
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[CPU] Split attention dispatch by head_dim alignment (#32161)
Signed-off-by: Rehan Khan <Rehan.Khan7@ibm.com>
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2026-02-03 19:37:15 -08:00 |
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203d0bc0c2
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[CPU] Improve CPU Docker build (#30953)
Signed-off-by: Maryam Tahhan <mtahhan@redhat.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2026-01-24 17:08:24 +00:00 |
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Fadi ArafehandGitHub
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744ef30484
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[CPU Backend] [Perf] Accelerate tensor-parallel/data-parallel inference across NUMA domains on Arm (#32792)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2026-01-22 18:55:23 +00:00 |
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Li, JiangandGitHub
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e3ab93c896
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[CPU] Refactor CPU fused MOE (#30531)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-12-18 14:36:49 +08:00 |
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Radu SalavatandGitHub
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180345807f
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[CMake][Build]: Remove unused ACL CMake env variables (#30339)
Signed-off-by: Radu Salavat <radu.salavat@arm.com>
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2025-12-10 04:27:19 +00:00 |
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Li, JiangandGitHub
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20852c8f4c
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[CPU] Refactor CPU WNA16 (#28826)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-11-19 10:32:00 +08:00 |
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86d15bfd8d
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[Hardware][PowerPC] Fix fp16 compilation error for Power in cpu attention backend and bump oneDNN version (#28535)
Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
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2025-11-13 13:32:21 +00:00 |
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Radu SalavatandGitHub
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d44fbbab0e
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[build][cmake]: Bundle static ACL and torch libgomp for CPU extension builds (#28059)
Signed-off-by: Radu Salavat <radu.salavat@arm.com>
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2025-11-13 05:43:08 +00:00 |
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Li, JiangandGitHub
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7f829be7d3
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[CPU] Refactor CPU attention backend (#27954)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-11-12 09:43:06 +08:00 |
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Abolfazl ShahbaziandGitHub
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d15afc1fd0
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Refactor CPU/GPU extension targets for CMake build (#28026)
Signed-off-by: Abolfazl Shahbazi <12436063+ashahba@users.noreply.github.com>
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2025-11-08 14:17:35 +08:00 |
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Fadi ArafehandGitHub
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a663f6ae64
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[cpu][perf] Fix low CPU utilization with VLLM_CPU_OMP_THREADS_BIND on AArch64 (#27415)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
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2025-10-27 11:14:55 +00:00 |
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163965d183
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[cpu] Dispatch un-quantized linear to oneDNN/ACL by default for AArch64 (#27183)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Michael Yang <Michael.Yang@arm.com>
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2025-10-21 02:02:58 +00:00 |
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ihb2032andGitHub
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086609de64
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fix(nix): Allow local oneDNN path to fix vLLM CPU build failure (#26401)
Signed-off-by: lyd1992 <liuyudong@iscas.ac.cn>
Signed-off-by: ihb2032 <1355790728@qq.com>
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2025-10-11 09:12:16 +00:00 |
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Nishidha PanpaliyaandGitHub
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8f8474fbe3
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[CI/Build] Fix ppc64le CPU build and tests (#22443)
Signed-off-by: Nishidha Panpaliya <nishidha.panpaliya@partner.ibm.com>
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2025-10-11 13:04:42 +08:00 |
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9705fba7b7
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[cpu][perf] Accelerate unquantized-linear for AArch64 through oneDNN/ACL and weight prepack (#25948)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2025-10-04 12:16:38 +08:00 |
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1e9a77e037
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[Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112)
Signed-off-by: chenlang <chen.lang5@zte.com.cn>
Co-authored-by: chenlang <10346245@zte.com.cn>
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2025-09-25 20:46:11 +08:00 |
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Nikhil GuptaandGitHub
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359d293006
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[fix]: add Arm 4bit fused moe support (#23809)
Signed-off-by: Nikhil Gupta <nikhil.gupta2@arm.com>
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2025-09-24 01:32:22 +00:00 |
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369a079568
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[Hardware][Apple-CPU] Disable OneDNN build for Apple Silicon (#24200)
Signed-off-by: ignaciosica <mignacio.sica@gmail.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2025-09-04 02:48:25 -07:00 |
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b78bed1bc5
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[Hardware][Mac] Fix the installation fail for Apple Silicon (CPU) (#23565)
Signed-off-by: oye93 <en.ouyang93@outlook.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2025-08-26 13:04:25 +00:00 |
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Li, JiangandGitHub
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7be5d113d8
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[CPU] Refactor CPU W8A8 scaled_mm (#23071)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-08-21 09:34:24 +08:00 |
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Ignacio SicaandGitHub
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5140f54b89
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[CI/Build] fix cpu_extension for apple silicon (#21195)
Signed-off-by: ignaciosica <mignacio.sica@gmail.com>
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2025-07-24 22:53:59 -07:00 |
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nishith-fujitsuandGitHub
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c7753a9809
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[Hardware][CPU] Vllm int8 quantization enablement for ARM CPU (#14129)
Signed-off-by: nishith-fujitsu <nishith.jaiswal@fujitsu.com>
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2025-07-10 15:59:04 +00:00 |
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