From 344609ab170a040fe5cfec74eac8db66cd344b6f Mon Sep 17 00:00:00 2001 From: "Li, Jiang" Date: Mon, 6 Jul 2026 16:24:24 +0800 Subject: [PATCH] [CI/Build] Fix pre-commit check (#47695) Signed-off-by: jiang1.li --- csrc/cpu/cpu_types_riscv_impl.hpp | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/csrc/cpu/cpu_types_riscv_impl.hpp b/csrc/cpu/cpu_types_riscv_impl.hpp index ae17272968f..70cb0ab52de 100644 --- a/csrc/cpu/cpu_types_riscv_impl.hpp +++ b/csrc/cpu/cpu_types_riscv_impl.hpp @@ -638,21 +638,20 @@ struct FP32Vec16 : public Vec { const uint32_t hi = static_cast(q >> 32); auto lane_ids = RVVI(__riscv_vid_v_u32, LMUL_256)(HALF); - auto shifts = - RVVI(__riscv_vsll_vx_u32, LMUL_256)(lane_ids, 2, HALF); + auto shifts = RVVI(__riscv_vsll_vx_u32, LMUL_256)(lane_ids, 2, HALF); auto packed_lo = RVVI(__riscv_vmv_v_x_u32, LMUL_256)(lo, HALF); auto idx_lo = RVVI(__riscv_vand_vx_u32, LMUL_256)( - RVVI(__riscv_vsrl_vv_u32, LMUL_256)(packed_lo, shifts, HALF), - 0xF, HALF); + RVVI(__riscv_vsrl_vv_u32, LMUL_256)(packed_lo, shifts, HALF), 0xF, + HALF); auto packed_hi = RVVI(__riscv_vmv_v_x_u32, LMUL_256)(hi, HALF); auto idx_hi = RVVI(__riscv_vand_vx_u32, LMUL_256)( - RVVI(__riscv_vsrl_vv_u32, LMUL_256)(packed_hi, shifts, HALF), - 0xF, HALF); + RVVI(__riscv_vsrl_vv_u32, LMUL_256)(packed_hi, shifts, HALF), 0xF, + HALF); - auto idx = RVVI4(__riscv_vcreate_v_u32, LMUL_256, _u32, - LMUL_512)(idx_lo, idx_hi); + auto idx = + RVVI4(__riscv_vcreate_v_u32, LMUL_256, _u32, LMUL_512)(idx_lo, idx_hi); reg = RVVI(__riscv_vrgather_vv_f32, LMUL_512)(lut.reg, idx, VEC_ELEM_NUM); } explicit FP32Vec16(const FP16Vec16& v);